1. Field of the Invention
The present invention is related to processing systems and processors, and more specifically to techniques for scheduling cache cleaning operations based on the distance between the least-recently-used (LRU) line and the first dirty line.
2. Description of Related Art
Cache performance can be improved when periodic flushing of dirty cache lines (i.e., “cache cleaning”) is performed. U.S. Patent Application Publication 2011/0276762 discloses a cache cleaner that schedules write bursts by collecting entries in a write queue. The entries are collected by determining if the number of dirty lines present in a congruence class exceeds a threshold and then scheduling write-back of one or more dirty lines if the threshold is exceeded.
While such a scheme will tend to minimize the number of dirty lines present in the cache, depending on actual accesses to lines within each congruence class, and depending on the number of new lines loaded in each congruence class, the cache-cleaning algorithm may still lead to excessive cast-out write-back penalties (waiting on space to be made in a congruence class for one or more new lines that are loaded).
Therefore, it would be desirable to provide a cache controller methodology that can more effectively control cache cleaning operations to provide improved cache performance and reduce the number of write operations issued to system memory.